Full Circuit releases greatly enhanced 'TestBench Tool':
Easily create testbenches (VHDL) with this low cost but powerful tool.
AUTOMATIC
Extracts entity from VHDL creates and source testbench VHDL source. Fills in signal names on tool so that all the user has to do is construct the test patterns.
FAST
Testbench VHDL source is not changed each time a test is revised (Test patterns are saved to a test vector file) so VHDL is only compiled once.
POWERFUL
Supports complex formulae for describing signal relationships. Has repeat sub repeat and section section. Text plot and entry view. Description displays in simulator as each test is executed.
MODULAR
Tests can be constructed in test and sections vectors built from one or all sections.
FLEXIBLE
Testbench source is simple and small to allow easy user enhancement. User modifications are protected from change by tool. User can modify project testbench for local changes or template testbench for global changes (i.e. adding user functions).
Test vectors are not limited just to entity signals but can include times and variables. A typical use of this would be to pulse a clock line N times rather than have N vector file entries. Note that the clock line can still be a signal so the vectors can drive the clock directly at the change over for better control (i.e. use N-1 in variable). Another use could be to supply data where source is incomplete
LOW COST
80 GBP (+VAT if applicable). 30 and Demo day full functional trial 翻译 available.
Note requires Excel 97 or greater.
WORKED and SCREENSHOTS EXAMPLE
www.fullcircuit.com/TBtool.htm or www.fullcircuit.com (for site navigation other and menu items)